* Claude review: None
[not found] <urn:uuid:1dc09086-5730-9ac1-a24a-5b34e9313865>
@ 2026-02-12 7:08 ` Claude Code Review Bot
0 siblings, 0 replies; 5+ messages in thread
From: Claude Code Review Bot @ 2026-02-12 7:08 UTC (permalink / raw)
To: dri-devel-reviews
Overall Series Review
Subject: None
Author: None
Patches: 0
Reviewed: 2026-02-12T17:08:27.857739
---
This 8-patch series adds support for batch allocation of multiple non-contiguous userptr ranges through the AMD KFD (Kernel Fusion Driver) interface. The implementation uses a single MMU notifier spanning the entire VA range with an interval tree to efficiently track which specific ranges are invalidated.
**Architecture Overview:**
The series extends the existing userptr allocation mechanism to handle multiple CPU VA ranges that map to a single contiguous GPU VA. The key design choice is using one `mmu_interval_notifier` covering [va_min, va_max] with an interval tree to filter invalidation events.
**Major Concerns:**
1. **UAPI Stability** - Patch 1 adds new UAPI structures without incrementing KFD_IOCTL_MINOR_VERSION
2. **Memory Safety** - Several error paths lack proper cleanup
3. **Locking Issues** - Complex interaction between multiple locks with potential for deadlocks
4. **Resource Leaks** - Interval tree nodes not always removed on error paths
5. **Data Structure Initialization** - Missing initialization of critical fields in error scenarios
**Series Strengths:**
- Well-structured patch split for review
- Handles complex MMU notifier scenarios
- Interval tree usage is appropriate for the problem
---
---
Generated by Claude Code Patch Reviewer
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v1 0/5] drm/panel: r61307/r69328: minor updates
@ 2026-02-15 8:51 Svyatoslav Ryhel
2026-02-15 9:01 ` Claude review: None Claude Code Review Bot
0 siblings, 1 reply; 5+ messages in thread
From: Svyatoslav Ryhel @ 2026-02-15 8:51 UTC (permalink / raw)
To: Neil Armstrong, Jessica Zhang, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Svyatoslav Ryhel
Cc: dri-devel, linux-kernel
Align r61307 with schema property and update r61307/r69328 according
to latest DRM changes.
Svyatoslav Ryhel (5):
drm/panel: r61307: align with schema property
drm/panel: r61307/r69328: convert to
drm_connector_helper_get_modes_fixed
drm/panel: r61307/r69328: remove redundant checks
drm/panel: r61307/r69328: return accumulated errors
drm/panel: r61307/r69328: convert to devm_mipi_dsi_attach
drivers/gpu/drm/panel/Kconfig | 2 +
drivers/gpu/drm/panel/panel-renesas-r61307.c | 40 ++++----------------
drivers/gpu/drm/panel/panel-renesas-r69328.c | 38 +++----------------
3 files changed, 15 insertions(+), 65 deletions(-)
--
2.51.0
^ permalink raw reply [flat|nested] 5+ messages in thread* Claude review: None
2026-02-15 8:51 [PATCH v1 0/5] drm/panel: r61307/r69328: minor updates Svyatoslav Ryhel
@ 2026-02-15 9:01 ` Claude Code Review Bot
0 siblings, 0 replies; 5+ messages in thread
From: Claude Code Review Bot @ 2026-02-15 9:01 UTC (permalink / raw)
To: dri-devel-reviews
Overall Series Review
Subject: None
Author: None
Patches: 0
Reviewed: 2026-02-15T19:01:01.789602
---
This 8-patch series adds batch userptr allocation support to amdkfd, allowing multiple non-contiguous CPU virtual address ranges to be mapped to a single contiguous GPU virtual address space via the existing `AMDKFD_IOC_ALLOC_MEMORY_OF_GPU` ioctl. The design uses a single MMU interval notifier covering the VA span with an interval tree for efficient range lookup during invalidation callbacks, which is a sound architectural choice.
The series has several significant issues that need addressing before it can be merged. The most critical are: (1) missing upper bound on `num_ranges` from userspace, allowing excessive kernel memory allocation; (2) the return value of `set_user_pages_batch()` is silently ignored in `init_user_pages_batch()`, which could lead to `ttm_bo_validate` operating on a corrupt pages array; (3) the error paths in `amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu_batch()` leak the mem limit reservation when `drm_vma_node_allow()` or `drm_gem_handle_create()` fails; and (4) the `size` parameter of `init_user_pages_batch()` is `uint32_t` but receives a `uint64_t` value, silently truncating sizes above 4GB.
Additionally, the patch references functions (`amdgpu_ttm_tt_get_user_pages_done`, `amdgpu_ttm_tt_discard_user_pages`) and uses types (`struct hmm_range *` in `user_range_info`) that do not match the upstream kernel tree's API (`amdgpu_hmm_range_alloc`/`amdgpu_hmm_range_free`, `struct amdgpu_hmm_range *`). This suggests the series was developed against an AMD staging tree with a different internal API, and needs reconciliation for upstream submission.
---
Generated by Claude Code Patch Reviewer
^ permalink raw reply [flat|nested] 5+ messages in thread
[parent not found: <urn:uuid:16f8d691-fa21-1457-9bc7-ecfc78a36673>]
* Claude review: None
[not found] <urn:uuid:16f8d691-fa21-1457-9bc7-ecfc78a36673>
@ 2026-02-13 4:37 ` Claude Code Review Bot
0 siblings, 0 replies; 5+ messages in thread
From: Claude Code Review Bot @ 2026-02-13 4:37 UTC (permalink / raw)
To: dri-devel-reviews
Overall Series Review
Subject: None
Author: None
Patches: 0
Reviewed: 2026-02-13T14:37:58.562243
---
This patch series adds support for batch userptr allocation in AMDKFD, allowing user-space to register multiple non-contiguous CPU virtual address ranges that map to a single contiguous GPU virtual address in one ioctl call. The series takes a measured approach by reusing the existing AMDKFD_IOC_ALLOC_MEMORY_OF_GPU ioctl with a new flag rather than introducing a new ioctl, minimizing the API surface change.
The architectural approach uses a single MMU interval notifier covering the span from the minimum to maximum address across all ranges, with an interval tree to efficiently filter which specific ranges are affected during invalidation callbacks. Individual ranges are tracked via the user_range_info structure which includes HMM ranges, validity flags, and interval tree nodes. The eviction/restore paths are unified to handle both single and batch allocations.
Several issues were identified that need to be addressed:
**Critical Issues:**
1. PATCH 6: In init_user_pages_batch, if get_user_pages_batch_locked fails for range i > 0, the error path doesn't properly release HMM ranges for ranges [0, i-1] that were successfully obtained. The err_cleanup_ranges path just sets range pointers to NULL without calling amdgpu_ttm_tt_get_user_pages_done.
2. PATCH 7: cleanup_userptr_resources doesn't set mem->range = NULL after calling amdgpu_ttm_tt_discard_user_pages in the single userptr cleanup path, creating a potential use-after-free if the range pointer is accessed after cleanup.
**Design Concerns:**
1. PATCH 8: kfd_copy_userptr_ranges doesn't validate an upper bound on num_ranges, allowing a user to request allocation of excessive kernel memory (though kvmalloc will eventually fail, there should be a reasonable limit like 4096 ranges).
2. PATCH 6: The initialization order in init_user_pages_batch registers the MMU notifier before obtaining pages for the ranges, creating a window where invalidation callbacks can race with initialization. While the current code handles this (valid flags start as false), this is a fragile pattern.
Overall, the series demonstrates good understanding of the HMM and MMU notifier subsystems, but the error handling needs strengthening to prevent resource leaks.
---
Generated by Claude Code Patch Reviewer
^ permalink raw reply [flat|nested] 5+ messages in thread
[parent not found: <urn:uuid:5d4d03cd-c007-cebf-9bba-1eefd9bcf3e2>]
* Claude review: None
[not found] <urn:uuid:5d4d03cd-c007-cebf-9bba-1eefd9bcf3e2>
@ 2026-02-12 21:38 ` Claude Code Review Bot
0 siblings, 0 replies; 5+ messages in thread
From: Claude Code Review Bot @ 2026-02-12 21:38 UTC (permalink / raw)
To: dri-devel-reviews
Overall Series Review
Subject: None
Author: None
Patches: 0
Reviewed: 2026-02-13T07:38:34.124137
---
This patch series adds support for batch userptr allocation to the AMDKFD driver, allowing multiple non-contiguous CPU virtual address ranges to be mapped to a single contiguous GPU virtual address. The implementation extends the existing AMDKFD_IOC_ALLOC_MEMORY_OF_GPU ioctl with a new flag (KFD_IOC_ALLOC_MEM_FLAGS_USERPTR_BATCH) and reuses the mmap_offset field to pass a pointer to an array of range descriptors.
The series takes a reasonable architectural approach by using a single MMU notifier covering the entire VA span and an interval tree to efficiently filter affected ranges during invalidation callbacks. The implementation integrates with existing userptr validation and eviction infrastructure.
However, there are several significant correctness issues that must be addressed:
1. **Critical resource leak on error paths**: Patch 6 has a severe bug where interval tree nodes are inserted but never removed on error paths, and the MMU notifier is not unregistered in all failure scenarios.
2. **Incorrect error path flow**: The error handling in init_user_pages_batch unconditionally falls through to release_pages even on success, and has goto targets that execute cleanup for resources that haven't been fully initialized.
3. **Interval tree cleanup race**: Patch 7's cleanup_userptr_resources removes interval tree nodes without holding any lock, creating a potential race with concurrent invalidation callbacks.
4. **Missing UAPI structure padding**: The new UAPI structures lack explicit padding, which could cause alignment issues on some architectures.
5. **Incomplete kgd_mem initialization**: The batch allocation path in patch 6 doesn't initialize user_ranges_itree before inserting nodes into it in one error scenario.
These issues are detailed in the per-patch reviews below.
---
Generated by Claude Code Patch Reviewer
^ permalink raw reply [flat|nested] 5+ messages in thread
[parent not found: <urn:uuid:ce20085f-ac6e-fe8e-f18d-f37b4adb464f>]
* Claude review: None
[not found] <urn:uuid:ce20085f-ac6e-fe8e-f18d-f37b4adb464f>
@ 2026-02-12 3:48 ` Claude Code Review Bot
0 siblings, 0 replies; 5+ messages in thread
From: Claude Code Review Bot @ 2026-02-12 3:48 UTC (permalink / raw)
To: dri-devel-reviews
Overall Series Review
Subject: None
Author: None
Patches: 0
Reviewed: 2026-02-12T13:48:40.869184
---
This patch series adds support for batch userptr allocation in the AMD KFD (Kernel Fusion Driver), allowing multiple non-contiguous CPU virtual address ranges to be mapped to a single contiguous GPU virtual address. The series introduces a new UAPI flag and data structures, implements interval tree-based range tracking, MMU notifier support, and integrates the functionality into the existing ioctl interface.
**Architecture Overview:**
The implementation uses a single MMU interval notifier covering the entire VA span (min to max address across all ranges), with an interval tree for efficient lookup of affected ranges during invalidation callbacks. Each range maintains its own HMM range and validity tracking.
**Key Concerns Identified:**
1. **Memory Leak Risk (CRITICAL)**: Patch 6 has a cleanup path that fails to free `mem->user_ranges` on several error paths after allocation.
2. **Race Condition**: Patch 5 (MMU notifier callback) increments `mem->invalid` without holding `mem->lock`, while other code paths hold this lock when accessing the field.
3. **Incomplete Error Handling**: Patch 6 continues execution after TTM validation failure instead of jumping to cleanup.
4. **Resource Management Issues**: Several cleanup paths don't properly handle partially initialized state.
5. **UAPI Design Concern**: Using bit 22 for the flag is safe but leaves a small window of available flag bits in the high region.
**Positive Aspects:**
- Good patch organization with logical separation of concerns
- Comprehensive integration with existing eviction/restore infrastructure
- Proper use of kernel interval tree API
- Reasonable test coverage described
---
---
Generated by Claude Code Patch Reviewer
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2026-02-12 7:08 ` Claude review: None Claude Code Review Bot
2026-02-15 8:51 [PATCH v1 0/5] drm/panel: r61307/r69328: minor updates Svyatoslav Ryhel
2026-02-15 9:01 ` Claude review: None Claude Code Review Bot
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2026-02-13 4:37 ` Claude Code Review Bot
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2026-02-12 21:38 ` Claude Code Review Bot
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