From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/bridge: ti-sn65dsi83: fix CHA_DSI_CLK_RANGE rounding Date: Fri, 27 Feb 2026 11:46:38 +1000 Message-ID: In-Reply-To: <20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-1-2e15f5a9a6a0@bootlin.com> References: <20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-0-2e15f5a9a6a0@bootlin.com> <20260226-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v1-1-2e15f5a9a6a0@bootlin.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **Verdict: Looks good.** The fix is correct. The register encoding is: ``` (CHA_DSI_CLK_RANGE * 5 MHz) <=3D DSI_CLK < ((CHA_DSI_CLK_RANGE + 1) * 5 MHz) ``` This means the register value should be the floor of `DSI_CLK / 5 MHz`. The= old code: ```c return DIV_ROUND_UP(clamp(..., 40000U, 500000U), 5000U); ``` rounds up, producing an off-by-one for any frequency that isn't an exact mu= ltiple of 5 MHz. The new code: ```c return clamp(..., 40000U, 500000U) / 5000U; ``` uses truncating integer division, which is the correct floor operation here= . The example in the commit message (437.1 MHz =E2=86=92 register 87 vs inc= orrect 88) clearly demonstrates the issue. Fixes tag and stable Cc are appropriate. --- --- Generated by Claude Code Patch Reviewer