Claude review: dt-bindings: display/msm/gpu: Drop redundant reg-names in one if:then:

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**Correctness: OK**

The top-level schema already defines `reg-names` at lines 59–64 of `gpu.yaml`:

```yaml
  reg-names:
    minItems: 1
    items:
      - const: kgsl_3d0_reg_memory
      - const: cx_mem
      - const: cx_dbgc
```

The removed block (inside the A6xx GMU `then:` clause, lines 443–448) is character-for-character identical:

```yaml
        reg-names:
          minItems: 1
          items:
            - const: kgsl_3d0_reg_memory
            - const: cx_mem
            - const: cx_dbgc
```

Since JSON Schema `allOf` creates an intersection of constraints, restating the same constraint in a `then:` block is a no-op. Removing it is the right thing to do.

**Contrast with the adreno-612.0 block (lines 400–408):** That `if:then:` also has a `reg-names` block, but it is *not* redundant — it works together with its sibling `reg: minItems: 3, maxItems: 3` to enforce that all three register regions must be present for that specific SoC. The top-level only requires `minItems: 1`, so the 612.0 override is meaningful and correctly left in place.

**Minor note:** The commit message says "Top-level reg-names defines already proper order for 'reg-names' with minItems: 1" — this is accurate, since the top-level `items` array already constrains the names and their ordering.

**No issues found.** 

Reviewed-by is warranted.

---
Generated by Claude Code Patch Reviewer