From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: dt-bindings: display/msm/gpu: Drop redundant reg-names in one if:then: Date: Tue, 03 Mar 2026 13:51:52 +1000 Message-ID: In-Reply-To: <20260301142033.88851-2-krzysztof.kozlowski@oss.qualcomm.com> References: <20260301142033.88851-2-krzysztof.kozlowski@oss.qualcomm.com> <20260301142033.88851-2-krzysztof.kozlowski@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **Correctness: OK** The top-level schema already defines `reg-names` at lines 59=E2=80=9364 of = `gpu.yaml`: ```yaml reg-names: minItems: 1 items: - const: kgsl_3d0_reg_memory - const: cx_mem - const: cx_dbgc ``` The removed block (inside the A6xx GMU `then:` clause, lines 443=E2=80=9344= 8) is character-for-character identical: ```yaml reg-names: minItems: 1 items: - const: kgsl_3d0_reg_memory - const: cx_mem - const: cx_dbgc ``` Since JSON Schema `allOf` creates an intersection of constraints, restating= the same constraint in a `then:` block is a no-op. Removing it is the righ= t thing to do. **Contrast with the adreno-612.0 block (lines 400=E2=80=93408):** That `if:= then:` also has a `reg-names` block, but it is *not* redundant =E2=80=94 it= works together with its sibling `reg: minItems: 3, maxItems: 3` to enforce= that all three register regions must be present for that specific SoC. The= top-level only requires `minItems: 1`, so the 612.0 override is meaningful= and correctly left in place. **Minor note:** The commit message says "Top-level reg-names defines alread= y proper order for 'reg-names' with minItems: 1" =E2=80=94 this is accurate= , since the top-level `items` array already constrains the names and their = ordering. **No issues found.**=20 Reviewed-by is warranted. --- Generated by Claude Code Patch Reviewer