Claude review: dt-bindings: display: msm: Fix reg ranges and clocks on Glymur

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**Typo: `clocks-names` should be `clock-names`**

The new conditional block adds:

```yaml
        clocks-names:
          minItems: 5
          maxItems: 6
```

The top-level property is defined as `clock-names` (line 101 of dp-controller.yaml), not `clocks-names`. Because this references a non-existent property, this constraint is silently ignored and has no effect.

To be fair, this is a **pre-existing bug** — all four existing `allOf` blocks in this file (lines 245, 267, 289, 309) have the same `clocks-names` typo. The patch is just following the existing (broken) pattern. Nevertheless, it would be good to fix it here or as a separate preparatory cleanup. As-is, none of the `clock-names` constraints in the entire file actually do anything.

**Commit message description inconsistency**

The commit message states:
> "the first three only have two streams wired up physically to the display subsystem, while the fourth controller has only one stream (SST)"

But then says:
> "allowing either one pixel clock, for the **third** DP controller, or two pixel clocks, for the rest of them"

These contradict each other. The first paragraph says the **fourth** controller is SST (one stream/one pixel clock), but the second says the **third** controller has one pixel clock. The description of which controller is SST-only should be clarified.

**Code change itself looks correct.** Removing `qcom,glymur-dp` from the 5-reg-entry group and adding a dedicated block requiring 9 reg entries and 5-6 clocks is the right approach to match the hardware description (4 ports + 2 MST link blocks = 9 reg ranges).

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