[PATCH v3 0/2] dt-bindings: display: msm: Fix Glymur DP controller reg ranges and clock

[PATCH v3 0/2] dt-bindings: display: msm: Fix Glymur DP controller reg ranges and clock

[Abel Vesa]

When display patches were initially submitted, they did not include the
p2, p3, mst2link and mst3link reg ranges. The devicetreedisplay nodes for
Glymur are still being reviewed and have not been merged yet.

This fix resulted from review comments on the devicetree nodes.

Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
Changes in v3:
- Fixed the reg ranges in the example node in qcom,glymur-mdss.yaml as well.
- Link to v2: https://patch.msgid.link/20260302-glymur-fix-dp-bindings-reg-clocks-v2-0-e99b6f871e3b@oss.qualcomm.com

Changes in v2:
- mistakenly sent without cover subject line. Please ignore.
- Link to v1: https://patch.msgid.link/20260227-glymur-fix-dp-bindings-reg-clocks-v1-1-99f7b42b43aa@oss.qualcomm.com

---
Abel Vesa (2):
      dt-bindings: display: msm: Fix reg ranges and clocks on Glymur
      dt-bindings: display: msm: Fix reg ranges for DP example node

 .../bindings/display/msm/dp-controller.yaml         | 21 ++++++++++++++++++++-
 .../bindings/display/msm/qcom,glymur-mdss.yaml      | 16 ++++++++++------
 2 files changed, 30 insertions(+), 7 deletions(-)
---
base-commit: 7c21b660e919698b10efa8bdb120f0f9bc3d3832
change-id: 20260227-glymur-fix-dp-bindings-reg-clocks-704d0ccbeef9

Best regards,
--  
Abel Vesa <abel.vesa@oss.qualcomm.com>

[PATCH v3 1/2] dt-bindings: display: msm: Fix reg ranges and clocks on Glymur

[Abel Vesa]

The Glymur platform has four DisplayPort controllers. All the
controllers support four streams (MST). However, the first three only
have two streams wired up physically to the display subsystem, while the
fourth controller has only one stream (SST).

So add a dedicated clause for Glymur compatible to enforce reg ranges to
describing all four streams while allowing either one pixel clock, for the
third DP controller, or two pixel clocks, for the rest of them.

Cc: <stable@vger.kernel.org> # v6.19
Fixes: 8f63bf908213 ("dt-bindings: display: msm: Document the Glymur DiplayPort controller")
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 .../bindings/display/msm/dp-controller.yaml         | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index ebda78db87a6..02ddfaab5f56 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -253,7 +253,6 @@ allOf:
             enum:
               # these platforms support 2 streams MST on some interfaces,
               # others are SST only
-              - qcom,glymur-dp
               - qcom,sc8280xp-dp
               - qcom,x1e80100-dp
     then:
@@ -310,6 +309,26 @@ allOf:
           minItems: 6
           maxItems: 8
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              # these platforms support 2 streams MST on some interfaces,
+              # others are SST only, but all controllers have 4 ports
+              - qcom,glymur-dp
+    then:
+      properties:
+        reg:
+          minItems: 9
+          maxItems: 9
+        clocks:
+          minItems: 5
+          maxItems: 6
+        clocks-names:
+          minItems: 5
+          maxItems: 6
+
 unevaluatedProperties: false
 
 examples:

-- 
2.48.1

[PATCH v3 2/2] dt-bindings: display: msm: Fix reg ranges for DP example node

[Abel Vesa]

Add the missing p2, p3, mst2link and mst3link register blocks to the DP
example node. This is now necessary since the DP schema has been fixed.

While at it, use actual addresses from the first controller instead of
made-up ones. This will align it with the description from SoC devicetree.

Cc: <stable@vger.kernel.org> # v6.19
Fixes: 1aee577bbc60 ("dt-bindings: display: msm: Document the Glymur Mobile Display SubSystem")
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
---
 .../bindings/display/msm/qcom,glymur-mdss.yaml           | 16 ++++++++++------
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/msm/qcom,glymur-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,glymur-mdss.yaml
index 2329ed96e6cb..64dde43373ac 100644
--- a/Documentation/devicetree/bindings/display/msm/qcom,glymur-mdss.yaml
+++ b/Documentation/devicetree/bindings/display/msm/qcom,glymur-mdss.yaml
@@ -176,13 +176,17 @@ examples:
                 };
             };
 
-            displayport-controller@ae90000 {
+            displayport-controller@af54000 {
                 compatible = "qcom,glymur-dp";
-                reg = <0xae90000 0x200>,
-                      <0xae90200 0x200>,
-                      <0xae90400 0x600>,
-                      <0xae91000 0x400>,
-                      <0xae91400 0x400>;
+                reg = <0xaf54000 0x200>,
+                      <0xaf54200 0x200>,
+                      <0xaf55000 0xc00>,
+                      <0xaf56000 0x400>,
+                      <0xaf57000 0x400>,
+                      <0xaf58000 0x400>,
+                      <0xaf59000 0x400>,
+                      <0xaf5a000 0x600>,
+                      <0xaf5b000 0x600>;
 
                 interrupt-parent = <&mdss>;
                 interrupts = <12>;

-- 
2.48.1

Re: [PATCH v3 1/2] dt-bindings: display: msm: Fix reg ranges and clocks on Glymur

[Rob Herring (Arm)]

On Mon, 02 Mar 2026 11:58:35 +0200, Abel Vesa wrote:
> The Glymur platform has four DisplayPort controllers. All the
> controllers support four streams (MST). However, the first three only
> have two streams wired up physically to the display subsystem, while the
> fourth controller has only one stream (SST).
> 
> So add a dedicated clause for Glymur compatible to enforce reg ranges to
> describing all four streams while allowing either one pixel clock, for the
> third DP controller, or two pixel clocks, for the rest of them.
> 
> Cc: <stable@vger.kernel.org> # v6.19
> Fixes: 8f63bf908213 ("dt-bindings: display: msm: Document the Glymur DiplayPort controller")
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---
>  .../bindings/display/msm/dp-controller.yaml         | 21 ++++++++++++++++++++-
>  1 file changed, 20 insertions(+), 1 deletion(-)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/msm/qcom,glymur-mdss.example.dtb: displayport-controller@ae90000 (qcom,glymur-dp): reg: [[183042048, 512], [183042560, 512], [183043072, 1536], [183046144, 1024], [183047168, 1024]] is too short
	from schema $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.kernel.org/project/devicetree/patch/20260302-glymur-fix-dp-bindings-reg-clocks-v3-1-8fe49ac1f556@oss.qualcomm.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH v3 2/2] dt-bindings: display: msm: Fix reg ranges for DP example node

[Dmitry Baryshkov]

On Mon, Mar 02, 2026 at 11:58:36AM +0200, Abel Vesa wrote:
> Add the missing p2, p3, mst2link and mst3link register blocks to the DP
> example node. This is now necessary since the DP schema has been fixed.
> 
> While at it, use actual addresses from the first controller instead of
> made-up ones. This will align it with the description from SoC devicetree.
> 
> Cc: <stable@vger.kernel.org> # v6.19
> Fixes: 1aee577bbc60 ("dt-bindings: display: msm: Document the Glymur Mobile Display SubSystem")
> Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> ---
>  .../bindings/display/msm/qcom,glymur-mdss.yaml           | 16 ++++++++++------
>  1 file changed, 10 insertions(+), 6 deletions(-)
> 
> -            displayport-controller@ae90000 {
> +            displayport-controller@af54000 {

Nice.


Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>



>                  compatible = "qcom,glymur-dp";
> -                reg = <0xae90000 0x200>,
> -                      <0xae90200 0x200>,
> -                      <0xae90400 0x600>,
> -                      <0xae91000 0x400>,
> -                      <0xae91400 0x400>;
> +                reg = <0xaf54000 0x200>,

-- 
With best wishes
Dmitry

Claude review: dt-bindings: display: msm: Fix Glymur DP controller reg ranges and clock

[Claude Code Review Bot]

Overall Series Review

Subject: dt-bindings: display: msm: Fix Glymur DP controller reg ranges and clock
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>
Patches: 5
Reviewed: 2026-03-03T13:37:09.334916

---

This is a 2-patch dt-bindings fix series for the Qualcomm Glymur DisplayPort controller. It separates the Glymur DP compatible from the existing `sc8280xp-dp`/`x1e80100-dp` group (which requires only 5 reg entries) into its own conditional block requiring 9 reg entries (to describe all 4 stream ports plus MST link blocks), and updates the example node in the MDSS binding to match.

The changes are straightforward and clearly motivated by review feedback on the actual devicetree nodes. There is one real bug (`clocks-names` typo) and an inconsistency in the commit message description worth flagging.

---
Generated by Claude Code Patch Reviewer

Claude review: dt-bindings: display: msm: Fix reg ranges and clocks on Glymur

[Claude Code Review Bot]

Patch Review

**Typo: `clocks-names` should be `clock-names`**

The new conditional block adds:

```yaml
        clocks-names:
          minItems: 5
          maxItems: 6
```

The top-level property is defined as `clock-names` (line 101 of dp-controller.yaml), not `clocks-names`. Because this references a non-existent property, this constraint is silently ignored and has no effect.

To be fair, this is a **pre-existing bug** — all four existing `allOf` blocks in this file (lines 245, 267, 289, 309) have the same `clocks-names` typo. The patch is just following the existing (broken) pattern. Nevertheless, it would be good to fix it here or as a separate preparatory cleanup. As-is, none of the `clock-names` constraints in the entire file actually do anything.

**Commit message description inconsistency**

The commit message states:
> "the first three only have two streams wired up physically to the display subsystem, while the fourth controller has only one stream (SST)"

But then says:
> "allowing either one pixel clock, for the **third** DP controller, or two pixel clocks, for the rest of them"

These contradict each other. The first paragraph says the **fourth** controller is SST (one stream/one pixel clock), but the second says the **third** controller has one pixel clock. The description of which controller is SST-only should be clarified.

**Code change itself looks correct.** Removing `qcom,glymur-dp` from the 5-reg-entry group and adding a dedicated block requiring 9 reg entries and 5-6 clocks is the right approach to match the hardware description (4 ports + 2 MST link blocks = 9 reg ranges).

---
Generated by Claude Code Patch Reviewer

Claude review: dt-bindings: display: msm: Fix reg ranges for DP example node

[Claude Code Review Bot]

Patch Review

This patch updates the example node in `qcom,glymur-mdss.yaml` to match the new 9-entry reg constraint from patch 1. The changes look correct:

```yaml
            displayport-controller@af54000 {
                reg = <0xaf54000 0x200>,   # ahb
                      <0xaf54200 0x200>,   # aux
                      <0xaf55000 0xc00>,   # link
                      <0xaf56000 0x400>,   # p0
                      <0xaf57000 0x400>,   # p1
                      <0xaf58000 0x400>,   # p2
                      <0xaf59000 0x400>,   # p3
                      <0xaf5a000 0x600>,   # mst2link
                      <0xaf5b000 0x600>;   # mst3link
```

- 9 reg entries, matching `minItems: 9` / `maxItems: 9` from patch 1.
- The unit address `@af54000` correctly matches the first reg entry base address.
- The commit message explains these are actual addresses from the first controller rather than made-up ones, which is good practice for binding examples.
- 6 clocks are listed in the example, which is within the 5-6 range from patch 1.

This patch is straightforward and correct. No issues beyond the dependency on patch 1's `clocks-names` typo (which would cause dtbs_check to not enforce the clock-names constraint on this example, but it also wasn't enforced before).

---
Generated by Claude Code Patch Reviewer

Claude review: dt-bindings: display: msm: Fix reg ranges and clocks on Glymur

[Claude Code Review Bot]

Overall Series Review

Subject: dt-bindings: display: msm: Fix reg ranges and clocks on Glymur
Author: Abel Vesa <abel.vesa@oss.qualcomm.com>
Patches: 2
Reviewed: 2026-03-04T07:43:55.780213

---

This is a single-patch fix for the Glymur DisplayPort DT bindings. It addresses two issues introduced in v6.19: the DP controller binding had incorrect register range constraints (5 instead of 9) by grouping Glymur with platforms that have a different register layout, and the MDSS example used wrong/incomplete register addresses. The fix is straightforward and correct — it moves `qcom,glymur-dp` out of the `sc8280xp-dp`/`x1e80100-dp` group into its own clause requiring all 9 register blocks, and updates the example to match.

There is one minor issue to flag: the patch perpetuates a pre-existing typo (`clocks-names` vs. `clock-names`).

**Verdict**: Looks good overall. One minor issue worth fixing.

---

---
Generated by Claude Code Patch Reviewer

Claude review: dt-bindings: display: msm: Fix reg ranges and clocks on Glymur

[Claude Code Review Bot]

Patch Review

**Commit message**: Clear and well-written. Good explanation of the hardware topology (four controllers, three with 2 streams, one SST). The `Fixes:` and `Cc: stable` tags are appropriate.

**dp-controller.yaml changes**:

The removal of `qcom,glymur-dp` from the existing 2-stream group and addition of a dedicated clause is the right approach. The new constraints match the hardware:
- `reg: minItems: 9, maxItems: 9` — correct for all 9 register blocks (ahb, aux, link, p0–p3, mst2link, mst3link), consistent with `qcom,sa8775p-dp` which has a similar 4-port topology.
- `clocks: minItems: 5, maxItems: 6` — correct for allowing SST (5 clocks) or 2-stream MST (6 clocks, with `stream_1_pixel`).

**Issue — `clocks-names` typo**:

```yaml
+        clocks-names:
+          minItems: 5
+          maxItems: 6
```

The property is defined as `clock-names` (line 101 of the file) and listed in the `required:` section as `clock-names` (line 184). The `clocks-names` used here (with the extra 's') doesn't match any defined property, so this constraint is silently ignored by the schema validator. This is a **pre-existing bug** — the same typo appears in all the other `allOf` clauses in this file — but since you're adding new code, this would be a good opportunity to use the correct name. At minimum it should be `clock-names:` in the new clause. Ideally a follow-up (or inclusion in this patch) would fix the other clauses too.

**qcom,glymur-mdss.yaml changes**:

The example update looks correct:

```yaml
-            displayport-controller@ae90000 {
+            displayport-controller@af54000 {
                 compatible = "qcom,glymur-dp";
-                reg = <0xae90000 0x200>,
-                      <0xae90200 0x200>,
-                      <0xae90400 0x600>,
-                      <0xae91000 0x400>,
-                      <0xae91400 0x400>;
+                reg = <0xaf54000 0x200>,
+                      <0xaf54200 0x200>,
+                      <0xaf55000 0xc00>,
+                      <0xaf56000 0x400>,
+                      <0xaf57000 0x400>,
+                      <0xaf58000 0x400>,
+                      <0xaf59000 0x400>,
+                      <0xaf5a000 0x600>,
+                      <0xaf5b000 0x600>;
```

- Addresses updated from made-up values to actual first-controller addresses.
- Link register block size corrected from `0x600` to `0xc00` (matching the sc7180 example and presumably the actual hardware).
- Four new register blocks added (p2, p3, mst2link, mst3link) to reach the required 9 entries.
- The `@` unit address in the node name matches the first reg entry. Good.

**Summary**: The fix is correct. The only issue is the `clocks-names` → `clock-names` typo that should be corrected before merging.

---
Generated by Claude Code Patch Reviewer