From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: dt-bindings: display: msm: Fix reg ranges and clocks on Glymur Date: Tue, 03 Mar 2026 13:37:09 +1000 Message-ID: In-Reply-To: <20260302-glymur-fix-dp-bindings-reg-clocks-v3-1-8fe49ac1f556@oss.qualcomm.com> References: <20260302-glymur-fix-dp-bindings-reg-clocks-v3-0-8fe49ac1f556@oss.qualcomm.com> <20260302-glymur-fix-dp-bindings-reg-clocks-v3-1-8fe49ac1f556@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **Typo: `clocks-names` should be `clock-names`** The new conditional block adds: ```yaml clocks-names: minItems: 5 maxItems: 6 ``` The top-level property is defined as `clock-names` (line 101 of dp-controll= er.yaml), not `clocks-names`. Because this references a non-existent proper= ty, this constraint is silently ignored and has no effect. To be fair, this is a **pre-existing bug** =E2=80=94 all four existing `all= Of` blocks in this file (lines 245, 267, 289, 309) have the same `clocks-na= mes` typo. The patch is just following the existing (broken) pattern. Never= theless, it would be good to fix it here or as a separate preparatory clean= up. As-is, none of the `clock-names` constraints in the entire file actuall= y do anything. **Commit message description inconsistency** The commit message states: > "the first three only have two streams wired up physically to the display= subsystem, while the fourth controller has only one stream (SST)" But then says: > "allowing either one pixel clock, for the **third** DP controller, or two= pixel clocks, for the rest of them" These contradict each other. The first paragraph says the **fourth** contro= ller is SST (one stream/one pixel clock), but the second says the **third**= controller has one pixel clock. The description of which controller is SST= -only should be clarified. **Code change itself looks correct.** Removing `qcom,glymur-dp` from the 5-= reg-entry group and adding a dedicated block requiring 9 reg entries and 5-= 6 clocks is the right approach to match the hardware description (4 ports += 2 MST link blocks =3D 9 reg ranges). --- Generated by Claude Code Patch Reviewer