Claude review: drm/msm/dsi: fix pclk rate calculation for bonded dsi

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**Correctness:** The fix is correct. With the example values in the commit message:
- Full width: `DIV_ROUND_UP(1904 * 8, 24) = DIV_ROUND_UP(15232, 24) = 635`
- Per-link: `DIV_ROUND_UP(952 * 8, 24) = DIV_ROUND_UP(7616, 24) = 318`, then `318 * 2 = 636`

The difference of 1 pixel matters because `dsi_timing_setup()` at line 1008 halves `hdisplay` before computing the compressed width per link, so the pclk rate calculation should match that behavior.

**Code review:**

The implementation is clean. The split-round-recombine pattern is easy to follow:

```c
hdisplay = mode->hdisplay;
if (is_bonded_dsi)
    hdisplay /= 2;

new_hdisplay = DIV_ROUND_UP(hdisplay * drm_dsc_get_bpp_int(dsc),
                dsc->bits_per_component * 3);

if (is_bonded_dsi)
    new_hdisplay *= 2;
```

**Minor observations:**

1. The commit message has a small typo: `new_full_display` should be `new_full_hdisplay` on the last line of the example to be consistent with the naming used just above it.

2. **Subtle divergence with `dsi_timing_setup`:** The commit message claims this "aligns with the hdisplay we program later in `dsi_timing_setup()`", but the two calculations are not strictly identical. `dsi_timing_setup()` uses `msm_dsc_get_bytes_per_line(dsc)` (i.e., `slice_count * slice_chunk_size`) divided by `bytes_per_pclk`, while `dsi_adjust_pclk_for_compression()` uses `DIV_ROUND_UP(hdisplay * bpp_int, bpc * 3)`. These formulas converge only when the DSC slice parameters produce the same effective ratio. The *rounding behavior* per half-link does align, which is what matters for this fix, but the comment could be slightly more precise about what "aligns" means — it's the halving of hdisplay before compression calculation, not the exact formula.

3. The function only handles VIDEO mode pclk calculation (the `FIXME` comment above notes CMD mode is different). This is fine since the `mult_frac` line at the end is only meaningful for video timing.

**Overall:** The patch correctly fixes a real bug where the pclk rate could be off by one compressed pixel's worth of clock cycles in bonded DSI + DSC configurations. Recommend applying with the typo fix in the commit message.

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Generated by Claude Code Patch Reviewer