Claude review: drm/msm/dsi: fix pclk calculation for bonded dsi

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**Correctness: Good**

The fix correctly addresses a real rounding discrepancy. Looking at `dsi_timing_setup()` (line 986-992 in the current tree), when `is_bonded_dsi` is true, `hdisplay /= 2` occurs *before* the DSC compression calculation at line 1035:

```c
hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), bytes_per_pclk);
```

So the timing path works on half the display width, meaning rounding is applied per-link. The pclk calculation should do the same, and this patch achieves that. The example in the commit message clearly demonstrates the off-by-one:

```
full_hdisplay = 1904, dsc_bpp = 8, bpc = 8
new_full_hdisplay = DIV_ROUND_UP(1904 * 8, 8 * 3) = 635

new_half_hdisplay = DIV_ROUND_UP(952 * 8, 8 * 3) = 318
new_full_display = 318 * 2 = 636
```

**Minor observations:**

1. The unrelated comment change from "dsi" to "DSI" on line 179 is a trivial style fix. It's fine to include but it's cosmetic noise in what is otherwise a Fixes-tagged patch:
```
-	 * the clock rates have to be split between the two dsi controllers.
+	 * the clock rates have to be split between the two DSI controllers.
```

2. The commit message says "v2: add a parameter desciption" — typo "desciption" should be "description", though this is below the `---` marker so it won't appear in the final git log.

3. There is a subtle assumption that `mode->hdisplay` is always even for bonded DSI (since `hdisplay /= 2` is integer division). This is the same assumption made in `dsi_timing_setup()` so it's consistent, but worth noting that odd hdisplay values in bonded mode would silently truncate a pixel.

**Overall: The patch looks correct and ready to merge.** The fix aligns the pclk calculation with what the hardware is actually programmed to do, and the logic is clean and well-commented.

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