From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: arm64: dts: qcom: talos: add the GPU SMMU node Date: Fri, 13 Mar 2026 14:34:42 +1000 Message-ID: In-Reply-To: <20260312-qcs615-spin-2-v8-1-fca38edcd6e6@oss.qualcomm.com> References: <20260312-qcs615-spin-2-v8-0-fca38edcd6e6@oss.qualcomm.com> <20260312-qcs615-spin-2-v8-1-fca38edcd6e6@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review **No issues found.** This is a straightforward SMMU node addition. - The compatible string chain `"qcom,qcs615-smmu-500", "qcom,adreno-smmu", "qcom,smmu-500", "arm,mmu-500"` follows the standard pattern for Adreno GPU SMMUs. - 1 global interrupt + 8 context bank interrupts (9 total) with `#global-interrupts = <1>` is correct. - 3 clocks (`mem`, `hlos`, `iface`) match established patterns (e.g., SDM845). - `dma-coherent` is appropriate for GPU SMMU on this SoC. - Node is correctly placed after `gpucc` in address order (`0x50a0000` > `0x5090000`). --- Generated by Claude Code Patch Reviewer