From mboxrd@z Thu Jan  1 00:00:00 1970
From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm: shmobile: Fix white screen after resume when LCDC is stopped
Date: Sun, 22 Mar 2026 04:28:52 +1000
Message-ID: <review-patch1-20260319083207.17195-1-phucduc.bui@gmail.com>
In-Reply-To: <20260319083207.17195-1-phucduc.bui@gmail.com>
References: <20260319083207.17195-1-phucduc.bui@gmail.com> <20260319083207.17195-1-phucduc.bui@gmail.com>
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Patch Review

**Correctness: Good.** The logic correctly distinguishes between the runnin=
g and stopped states:

```c
ldcnt2r =3D lcdc_read(sdev, LDCNT2R);

if (ldcnt2r & LDCNT2R_DO) {
    lcdc_write_mirror(sdev, LDSA1R, sstate->dma[0]);
    ...
    lcdc_write(sdev, LDRCNTR, lcdc_read(sdev, LDRCNTR) ^ LDRCNTR_MRS);
} else {
    lcdc_write(sdev, LDSA1R, sstate->dma[0]);
    ...
}
```

When DO=3D0, `lcdc_write()` is used which writes to both the base register =
and `reg + LCDC_SIDE_B_OFFSET` (since LDSA1R and LDSA2R are banked register=
s per `lcdc_is_banked()`). This primes both register sets, avoiding the whi=
te screen.

When DO=3D1, the existing mirror-write + MRS toggle path is preserved, main=
taining the correct double-buffered update behavior during normal operation.

**Minor observations:**
- The `LDRCNTR` toggle is correctly omitted in the DO=3D0 path since there'=
s no need to request a register set switch when the controller is stopped.
- The YUV handling (LDSA2R) is consistently handled in both branches.
- No concerns about atomicity =E2=80=94 in the DO=3D0 case the controller i=
s stopped so there's no race with hardware reading registers.

**Commit message:** Clear, well-written, explains the root cause and the fi=
x. The changelog for v2/v3 is properly formatted below the `---` separator.

**Verdict: No issues found.** This is a clean, correct, and well-tested fix.

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