From mboxrd@z Thu Jan  1 00:00:00 1970
From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/msm/a8xx: Fix the ticks used in submit traces
Date: Wed, 25 Mar 2026 07:32:07 +1000
Message-ID: <review-patch1-20260324-a8xx-gpu-batch2-v1-1-fc95b8d9c017@oss.qualcomm.com>
In-Reply-To: <20260324-a8xx-gpu-batch2-v1-1-fc95b8d9c017@oss.qualcomm.com>
References: <20260324-a8xx-gpu-batch2-v1-0-fc95b8d9c017@oss.qualcomm.com> <20260324-a8xx-gpu-batch2-v1-1-fc95b8d9c017@oss.qualcomm.com>
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Patch Review

Good cleanup. The `get_timestamp()` interface change from `int (*get_timest=
amp)(struct msm_gpu *gpu, uint64_t *value)` to `u64 (*get_timestamp)(struct=
 msm_gpu *gpu)` is a nice simplification =E2=80=94 the function never actua=
lly failed.

The new `read_gmu_ao_counter()` in a8xx_gpu.c uses the classic hi-lo-hi pat=
tern for 64-bit reads:
```c
do {
    count_hi =3D gmu_read(&a6xx_gpu->gmu, REG_A8XX_GMU_ALWAYS_ON_COUNTER_H);
    count_lo =3D gmu_read(&a6xx_gpu->gmu, REG_A8XX_GMU_ALWAYS_ON_COUNTER_L);
    temp =3D gmu_read(&a6xx_gpu->gmu, REG_A8XX_GMU_ALWAYS_ON_COUNTER_H);
} while (unlikely(count_hi !=3D temp));
```
This correctly avoids the OOB set/clear that the old code required. The reg=
ister XML updates for the A8XX variant offsets look correct.

**Nit:** The cast in `adreno_gpu.c` is unnecessary:
```c
*value =3D (uint64_t) adreno_gpu->funcs->get_timestamp(gpu);
```
The function already returns `u64`, so the cast is redundant.

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