Claude review: drm/panel-edp: Add 2 panels used by MT8186 Chromebooks

[Claude Code Review Bot <claude-review@example.com>]

Patch Review

**EDID verification:**
- **CSW PNB601LS1-2**: EDID bytes 8-9 = `0e 77` (CSW), product code bytes 10-11 = `0a 11` → little-endian = `0x110A`. Matches the entry.
- **LGD LP116WHA-SPB1**: EDID bytes 8-9 = `30 e4` (LGD), product code bytes 10-11 = `fe 07` → little-endian = `0x07FE`. Matches the entry.

**Sort order:** Both entries are inserted in the correct hex-sorted position within their manufacturer groups.

**Delay values:**
- The LGD entry uses `&delay_200_500_e200_d200`, which is consistent with every other LGD panel in the table. No concerns there.
- The CSW entry uses `&delay_200_500_e50`. The other CSW panels in the MNB601LS1 family use different delays:
  - `0x1100` MNB601LS1-1 → `delay_200_500_e80_d50`
  - `0x1103` MNB601LS1-3 → `delay_200_500_e80_d50`
  - `0x1104` MNB601LS1-4 → `delay_200_500_e50_d100`

  The new PNB601LS1-2 uses `delay_200_500_e50` (no deassert delay). This is a different panel family name prefix (PNB vs MNB), so different timing could be expected, but it would be good for the author to confirm the power-off-to-on delay (`d`) and enable delay (`e`) values were verified against the panel datasheet.

**Minor nit:** The commit subject says "2 panels" but doesn't mention the specific platform context in the diff itself. This is fine for a panel-edp data patch.

**No functional issues found.** The patch is correct and ready to merge, assuming the delay values for the CSW panel have been validated on hardware.

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Generated by Claude Code Patch Reviewer