From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/panel-edp: Add 2 panels used by MT8186 Chromebooks Date: Wed, 25 Mar 2026 07:01:00 +1000 Message-ID: In-Reply-To: <20260324061444.242917-1-terry_hsiao@compal.corp-partner.google.com> References: <20260324061444.242917-1-terry_hsiao@compal.corp-partner.google.com> <20260324061444.242917-1-terry_hsiao@compal.corp-partner.google.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **EDID verification:** - **CSW PNB601LS1-2**: EDID bytes 8-9 =3D `0e 77` (CSW), product code bytes= 10-11 =3D `0a 11` =E2=86=92 little-endian =3D `0x110A`. Matches the entry. - **LGD LP116WHA-SPB1**: EDID bytes 8-9 =3D `30 e4` (LGD), product code byt= es 10-11 =3D `fe 07` =E2=86=92 little-endian =3D `0x07FE`. Matches the entr= y. **Sort order:** Both entries are inserted in the correct hex-sorted positio= n within their manufacturer groups. **Delay values:** - The LGD entry uses `&delay_200_500_e200_d200`, which is consistent with e= very other LGD panel in the table. No concerns there. - The CSW entry uses `&delay_200_500_e50`. The other CSW panels in the MNB6= 01LS1 family use different delays: - `0x1100` MNB601LS1-1 =E2=86=92 `delay_200_500_e80_d50` - `0x1103` MNB601LS1-3 =E2=86=92 `delay_200_500_e80_d50` - `0x1104` MNB601LS1-4 =E2=86=92 `delay_200_500_e50_d100` The new PNB601LS1-2 uses `delay_200_500_e50` (no deassert delay). This is= a different panel family name prefix (PNB vs MNB), so different timing cou= ld be expected, but it would be good for the author to confirm the power-of= f-to-on delay (`d`) and enable delay (`e`) values were verified against the= panel datasheet. **Minor nit:** The commit subject says "2 panels" but doesn't mention the s= pecific platform context in the diff itself. This is fine for a panel-edp d= ata patch. **No functional issues found.** The patch is correct and ready to merge, as= suming the delay values for the CSW panel have been validated on hardware. --- Generated by Claude Code Patch Reviewer