From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/amdgpu: replace PASID IDR with XArray Date: Tue, 31 Mar 2026 17:18:18 +1000 Message-ID: In-Reply-To: <20260330113501.25654-1-mikhail.v.gavrilov@gmail.com> References: <20260330113501.25654-1-mikhail.v.gavrilov@gmail.com> <20260330113501.25654-1-mikhail.v.gavrilov@gmail.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **Commit message quality:** Excellent. The two bugs are clearly described, = the hardirq call chain is documented, and the real-world trigger scenario (= RX 7900 XTX + Vulkan/Proton) is mentioned. The Fixes/Cc-stable tags are cor= rect. **Code review:** The XArray conversion is mechanically correct: - `DEFINE_XARRAY_ALLOC` is the right macro for an XArray that will use `xa_= alloc` / `__xa_alloc_cyclic`. - The `static u32 amdgpu_pasid_xa_next` cursor for cyclic allocation is cor= rect =E2=80=94 `__xa_alloc_cyclic` requires a caller-managed `next` variabl= e. - `xa_lock_irqsave` / `xa_unlock_irqrestore` properly handles the hardirq c= ontext issue (bug #2). - `GFP_ATOMIC` is correct since allocation happens under the xa_lock (bug #= 1 fix). - `xa_mk_value(0)` as the stored entry is fine =E2=80=94 XArray treats `NUL= L` as "empty slot", so a non-NULL value is needed to mark the PASID as allo= cated. Using an internal value entry avoids memory allocation for the store= d pointer. - The limit `XA_LIMIT(1, (1U << bits) - 1)` correctly maps the old IDR rang= e `[1, 1U << bits)` =E2=80=94 IDR's `end` parameter is exclusive while XA_L= IMIT's max is inclusive, so `(1U << bits) - 1` is the right translation. **Minor nit on return value handling:** ```c r =3D __xa_alloc_cyclic(&amdgpu_pasid_xa, &pasid, xa_mk_value(0), XA_LIMIT(1, (1U << bits) - 1), &amdgpu_pasid_xa_next, GFP_ATOMIC); xa_unlock_irqrestore(&amdgpu_pasid_xa, flags); if (r >=3D 0) { trace_amdgpu_pasid_allocated(pasid); return pasid; } return r; ``` `__xa_alloc_cyclic` returns 0 on success, 1 if it wrapped around (both >=3D= 0), or a negative errno. The `r >=3D 0` check is correct. However, note th= at `__xa_alloc_cyclic` can return 1 when the allocation wrapped, which is n= ot an error =E2=80=94 the code handles this correctly since `r >=3D 0` cove= rs both cases. Good. **Cleanup function:** ```c void amdgpu_pasid_mgr_cleanup(void) { xa_destroy(&amdgpu_pasid_xa); } ``` `xa_destroy()` does not require external locking =E2=80=94 it frees interna= l nodes and resets the array. This is correct and simpler than the IDR vers= ion which took the spinlock around `idr_destroy()`. At cleanup time there s= hould be no concurrent access anyway. **No issues found.** The patch is a clean, correct conversion that fixes bo= th bugs. The only potential concern is that `GFP_ATOMIC` is more restrictiv= e than `GFP_KERNEL` (could fail under memory pressure), but this is unavoid= able when allocating under a lock that may be taken in IRQ context, and PAS= ID allocation failures are already handled by callers. --- Generated by Claude Code Patch Reviewer