From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: accel/ivpu: Fix swapped register names in pwr_island_drive functions Date: Thu, 23 Apr 2026 08:38:04 +1000 Message-ID: In-Reply-To: <20260421093907.37304-1-karol.wachowski@linux.intel.com> References: <20260421093907.37304-1-karol.wachowski@linux.intel.com> <20260421093907.37304-1-karol.wachowski@linux.intel.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **Assessment: Correct, no issues.** The fix is a clean symmetric swap. In `pwr_island_drive_37xx`: ```c - u32 val =3D REGV_RD32(VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0); + u32 val =3D REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0); ``` and the field name changes from `CSS_CPU` to `MSS_CPU` (matching the 37xx h= eader definition). In `pwr_island_drive_40xx`, the inverse swap is applied. I verified in the register definition headers: - `ivpu_hw_37xx_reg.h:98`: `VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0 =3D 0x00030= 024u` with `MSS_CPU_MASK =3D BIT_MASK(3)` - `ivpu_hw_40xx_reg.h:107`: `VPU_40XX_HOST_SS_AON_PWR_ISLAND_EN0 =3D 0x0003= 0024u` with `CSS_CPU_MASK =3D BIT_MASK(3)` The `REG_SET_FLD` / `REG_CLR_FLD` macros in `ivpu_hw_reg_io.h` concatenate = `REG##_##FLD##_MASK` to form the mask name, so the register name and field = name must be from the same generation's header. Before this patch they happ= ened to work only because the offsets and bit positions are identical acros= s generations. **Minor notes:** - The commit message could mention a `Fixes:` tag pointing to the commit th= at introduced the bug, which helps stable-tree backport tracking. However, = since the bug is cosmetic, this is not strictly necessary. - No functional change =E2=80=94 safe to apply as-is. --- Generated by Claude Code Patch Reviewer