From mboxrd@z Thu Jan  1 00:00:00 1970
From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/msm/a8xx: Fix RSCC offset
Date: Sat, 16 May 2026 12:51:46 +1000
Message-ID: <review-patch1-20260513-glymur-gpu-dt-v4-1-f83832c3bc9a@oss.qualcomm.com>
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Patch Review

**Purpose:** Changes the RSCC base from `gmu->mmio + 0x19000` (GMU-relative=
) to `gpu->mmio + 0x50000` (GPU-relative) for A8xx GPUs.

This fix looks correct. Based on the Glymur DT in patch 5, the GPU register=
 space covers `0x03d00000` (size `0x6c000`) and GMU is at `0x03d6c000`. The=
 old code pointed RSCC at `0x03d85000` (GMU+0x19000), while the fix targets=
 `0x03d50000` (GPU+0x50000), which falls squarely within the GPU's `kgsl_3d=
0_reg_memory` range. The `gpu` local variable is already initialized at lin=
e 2236 of `a6xx_gmu.c` and its `mmio` is mapped before GMU init, so this is=
 safe.

The cleanup path in `a6xx_gmu_remove()` sets `gmu->rscc =3D NULL` without t=
rying to iounmap it separately, which is correct since it's now an offset i=
nto `gpu->mmio`.

**Minor nit:** The comment has a typo =E2=80=94 extra space before the comm=
a:

```c
 * On a8xx , RSCC lives at GPU base + 0x50000, which falls
```

Should be:

```c
 * On a8xx, RSCC lives at GPU base + 0x50000, which falls
```

The Fixes tag pointing to `50e8a557d8d3 ("drm/msm/a8xx: Add support for A8x=
 GMU")` is appropriate.

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