From mboxrd@z Thu Jan  1 00:00:00 1970
From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/scdc-helper: Add scdc_status debugfs entry
Date: Mon, 25 May 2026 21:49:33 +1000
Message-ID: <review-patch1-20260520-scdc-link-health-v2-1-511af18cd64b@collabora.com>
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References: <20260520-scdc-link-health-v2-0-511af18cd64b@collabora.com> <20260520-scdc-link-health-v2-1-511af18cd64b@collabora.com>
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Patch Review

This is the bulk of the series =E2=80=94 adds `drm_scdc_read_state`, status=
 flag structs, error counter reading, and the debugfs show function. Genera=
lly well done, but a few issues:

**1. Inappropriate comment (medium)**

```c
/* why in the fucking fuck does this return a ssize_t */
ret =3D drm_scdc_read(connector->ddc, SCDC_ERR_DET_0_L, buf, ARRAY_SIZE(buf=
));
```

This comment is not appropriate for the kernel tree. If you want to note th=
e type mismatch, something like `/* drm_scdc_read returns ssize_t but 0 on =
success */` would be acceptable.

**2. Bitfield union portability on big-endian (medium)**

```c
struct drm_scdc_status_flags {
	union {
		struct {
			bool clock_detected : 1;
			bool ch0_locked : 1;
			bool ch1_locked : 1;
			bool ch2_locked : 1;
			...
		} flags __packed;
		u8 data;
	} status0;
```

GCC orders bitfields from LSB on little-endian targets but from MSB on big-=
endian targets. On a big-endian system, `clock_detected` would map to bit 7=
 instead of bit 0 (where `SCDC_CLOCK_DETECT` is defined). This means the bi=
tfield-to-register mapping is wrong on big-endian. Consider using explicit =
bit masks (the header already defines `SCDC_CLOCK_DETECT`, `SCDC_CH0_LOCK`,=
 etc.) and accessor functions instead, or adding an endianness guard/commen=
t explaining why this is acceptable.

**3. Doc typo**

```c
/** @scramling_enabled: true if TMDS scrambling is on */
```

Should be `@scrambling_enabled`.

**4. Status reading clears update flag before reading the register**

In `drm_scdc_read_status0_flags`:
```c
ret =3D drm_scdc_writeb(connector->ddc, SCDC_UPDATE_0, SCDC_STATUS_UPDATE);
if (ret)
    return ret;

return drm_scdc_readb(connector->ddc, SCDC_STATUS_FLAGS_0, &flags->status0.=
data);
```

The update flag is cleared (by writing 1 to it) *before* reading the status=
 register. There's a small race window where the sink could update the stat=
us between the clear and the read, meaning the source wouldn't know to re-r=
ead later. For debugfs this is fine, but since `drm_scdc_read_status0_flags=
` is exported as a general-purpose API, consider documenting this behavior =
or swapping the order (read first, then clear). The same pattern appears in=
 `drm_scdc_read_error_counters` with `SCDC_CED_UPDATE`, though for CED clea=
ring before reading is the spec-mandated behavior, so that one is correct.

**5. Minor: `status1` bitfields are all reserved and unused**

The `status1` member in `drm_scdc_status_flags` has 8 reserved bool bitfiel=
ds but is never read or displayed in this patch. This is fine since patch 3=
 replaces them, but in isolation patch 1 adds dead code.

---
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