From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: dt-bindings: display: rockchip: analogix-dp: Fix hclk as third clock for RK3588 Date: Mon, 25 May 2026 20:40:12 +1000 Message-ID: In-Reply-To: <20260521080835.1362416-2-damon.ding@rock-chips.com> References: <20260521080835.1362416-1-damon.ding@rock-chips.com> <20260521080835.1362416-2-damon.ding@rock-chips.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review Good approach. Moving from a single global `clock-names` items list to per-= compatible `if/then` constraints properly captures the reality that differe= nt SoCs have different third-clock semantics (`grf` for RK3399 vs `hclk` fo= r RK3588). The commit message is well-written and explains the *why* clearly =E2=80=94= the distinction between `grf` (toggled dynamically for register access) an= d `hclk` (must remain enabled for both GRF access and video datapath gating= ). No issues. --- Generated by Claude Code Patch Reviewer