From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/a8xx: Fix RSCC offset Date: Mon, 25 May 2026 18:58:50 +1000 Message-ID: In-Reply-To: <20260522-glymur-gpu-dt-v5-1-562c406b210c@oss.qualcomm.com> References: <20260522-glymur-gpu-dt-v5-0-562c406b210c@oss.qualcomm.com> <20260522-glymur-gpu-dt-v5-1-562c406b210c@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review **Summary:** Changes the RSCC base address from `gmu->mmio + 0x19000` to `gpu->mmio + 0x50000` for A8xx GPUs. This fix correctly changes both the base pointer and the offset. On A8xx the RSCC block lives in the GPU register space rather than the GMU's, so using `gpu->mmio` instead of `gmu->mmio` is the right thing to do. Verified that `gpu` (a `struct msm_gpu *`) is in scope in `a6xx_gmu_init()` (line 2236 of the current tree) and that `gpu->mmio` is initialized by `adreno_gpu_init()` before `a6xx_gmu_init()` is called. The offset 0x50000 falls within the GPU's `kgsl_3d0_reg_memory` range (size 0x6c000 per patch 4), so the access is within bounds. Has an appropriate `Fixes:` tag. **Minor nit:** Extra space in the comment: ```c + * On a8xx , RSCC lives at GPU base + 0x50000, which falls ``` Should be `On a8xx,` (no space before comma). --- Generated by Claude Code Patch Reviewer