From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/dp: fix HPD state status bit shift value Date: Mon, 25 May 2026 17:13:07 +1000 Message-ID: In-Reply-To: <20260524-hpd-refactor-v6-1-cf3ab488dd7b@oss.qualcomm.com> References: <20260524-hpd-refactor-v6-0-cf3ab488dd7b@oss.qualcomm.com> <20260524-hpd-refactor-v6-1-cf3ab488dd7b@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review Clean bugfix. The HPD_INT_STATUS register uses 3 bits (not 4) for the state status field: ```c -#define DP_DP_HPD_STATE_STATUS_BITS_MASK (0x0000000F) -#define DP_DP_HPD_STATE_STATUS_BITS_SHIFT (0x1C) +#define DP_DP_HPD_STATE_STATUS_BITS_MASK (0x00000007) +#define DP_DP_HPD_STATE_STATUS_BITS_SHIFT (0x1D) ``` Correct: 3-bit field at bits [31:29] = mask 0x7 with shift 0x1D. Has Fixes tag. **No issues.** --- --- Generated by Claude Code Patch Reviewer