From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: dt-bindings: display: rockchip: analogix-dp: Fix hclk as third clock for RK3588 Date: Wed, 27 May 2026 13:55:44 +1000 Message-ID: In-Reply-To: <20260527024336.191433-2-damon.ding@rock-chips.com> References: <20260527024336.191433-1-damon.ding@rock-chips.com> <20260527024336.191433-2-damon.ding@rock-chips.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review Good fix. The per-SoC clock-name constraints in `allOf` blocks are the corr= ect approach =E2=80=94 the top-level definition allows both `grf` and `hclk= ` as the third clock, while per-compatible blocks narrow it: ```yaml - enum: - grf - hclk ``` The RK3288 block correctly limits to 2 clocks, RK3399 constrains to `grf`, = and RK3588 constrains to `hclk`. The commit message clearly explains **why*= * `hclk` is a different clock from `grf` (GRF access vs. GRF access + video= datapath gating), which is important context. No issues. --- Generated by Claude Code Patch Reviewer