From mboxrd@z Thu Jan  1 00:00:00 1970
From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/v3d: Wait for pending L2T flush before cleaning caches
Date: Thu, 04 Jun 2026 15:23:15 +1000
Message-ID: <review-patch1-20260530-v3d-fix-rpi4-freezes-v1-1-c2c8307da6ce@igalia.com>
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References: <20260530-v3d-fix-rpi4-freezes-v1-0-c2c8307da6ce@igalia.com> <20260530-v3d-fix-rpi4-freezes-v1-1-c2c8307da6ce@igalia.com>
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Patch Review

**Purpose:** On pre-V3D 7.1 hardware, `v3d_clean_caches()` writes to `V3D_C=
TL_L2TCACTL` without first checking if a prior L2T flush (`V3D_L2TCACTL_L2T=
FLS`) is still in flight. This can clobber bits in the register and cause c=
ache inconsistencies.

**Code added in `v3d_gem.c:209-215`:**
```c
/* GFXH-1897: Ensure pending flushes complete before writing L2TCACTL */
if (v3d->ver < V3D_GEN_71) {
    if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) &
                   V3D_L2TCACTL_L2TFLS), 100)) {
        drm_err(dev, "Timeout waiting for L2T clean\n");
    }
}
```

**Analysis:**
- The GFXH-1897 workaround reference is good practice for hardware errata.
- The version guard (`v3d->ver < V3D_GEN_71`) is appropriate =E2=80=94 the =
comment in `v3d_flush_l2t()` at line 179 already notes the L2TFLS busy-bit =
behavior, and this new wait ensures the previous flush has drained before a=
 clean overwrites the register.
- The 100ms timeout is consistent with all other `wait_for` calls in this f=
ile.
- The placement before the `V3D_L2TCACTL_TMUWCF` write is correct =E2=80=94=
 it protects the first write to L2TCACTL.
- The Fixes tag points to the original compute dispatch commit that introdu=
ced `v3d_clean_caches`, which is correct =E2=80=94 this is a pre-existing b=
ug independent of PM.
- The `Cc: stable@vger.kernel.org` is appropriate.

**Minor note:** The error message "Timeout waiting for L2T clean" could be =
confused with the identical message at line 231 (the later L2TFLS clean wai=
t). Consider making this one distinct, e.g., "Timeout waiting for pending L=
2T flush" =E2=80=94 but this is cosmetic and not blocking.

**Verdict: Looks correct.**

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