From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/rockchip: dsi: Add maximum per lane bit rate calculation Date: Thu, 04 Jun 2026 11:57:42 +1000 Message-ID: In-Reply-To: <20260603033532.164-2-kernel@airkyi.com> References: <20260603033532.164-1-kernel@airkyi.com> <20260603033532.164-2-kernel@airkyi.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **Status: Looks good overall** This patch replaces the hard-coded max lane rate (previously derived from `= dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps`, which was always 1500 Mbps) w= ith a per-chip `max_bit_rate_per_lane` field. The values assigned per SoC a= re: - PX30, RK3128, RV1126: 1000 Mbps (1000000000UL) - RK3568: 1200 Mbps (1200000000UL) - RK3288, RK3368, RK3399, RK3506: 1500 Mbps (1500000000UL) The unit conversion is correct: ```c max_mbps =3D dsi->cdata->max_bit_rate_per_lane / USEC_PER_SEC; ``` `USEC_PER_SEC` =3D 1,000,000, so e.g. 1,500,000,000 / 1,000,000 =3D 1500 Mb= ps. This is correct. **Minor observation**: For chips that previously had a max of 1500 from `dp= pa_map`, this is a no-op. For PX30/RK3128/RV1126, this is now a *functional= change* that lowers the max from 1500 to 1000 Mbps =E2=80=94 this will cau= se the "out of range" error path to trigger earlier on those chips, which i= s actually the correct behavior since they can't actually drive 1500 Mbps. No issues found in this patch. --- --- Generated by Claude Code Patch Reviewer