From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/panel: Enable DSC for Visionox VTDR6130 panel Date: Fri, 05 Jun 2026 06:24:33 +1000 Message-ID: In-Reply-To: <20260604-topic-sm8x50-vtdr6130-dsc-v1-1-09bcd1dff1fb@linaro.org> References: <20260604-topic-sm8x50-vtdr6130-dsc-v1-0-09bcd1dff1fb@linaro.org> <20260604-topic-sm8x50-vtdr6130-dsc-v1-1-09bcd1dff1fb@linaro.org> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review **Author:** Jun Nie, signed-off by Neil Armstrong. This patch adds structured DSC configuration and sends the PPS via the stan= dard MIPI DCS Picture Parameter Set command. **DSC configuration (probe):** ```c + ctx->dsc.dsc_version_major =3D 0x1; + ctx->dsc.dsc_version_minor =3D 0x2; + ctx->dsc.slice_height =3D 40; + ctx->dsc.slice_width =3D 540; + ctx->dsc.slice_count =3D 2; + ctx->dsc.bits_per_component =3D 8; + ctx->dsc.bits_per_pixel =3D 8 << 4; + ctx->dsc.block_pred_enable =3D true; + + dsi->dsc =3D &ctx->dsc; ``` These parameters are consistent with the existing hardcoded PPS blob in the= 0x70 vendor register (which decodes to: DSC 1.2, pic_height=3D2400, pic_wi= dth=3D1080, slice_height=3D40, slice_width=3D540). The `bits_per_pixel =3D = 8 << 4` (128, i.e. 8.0 bpp with 4 fractional bits) matches the pattern used= across all other panel drivers. The remaining DSC parameters (RC model, in= itial offset, etc.) are populated by the MSM DSI host driver via `dsi_popul= ate_dsc_params()` when it sees `dsi->dsc` is set. **DSC enable command:** ```c + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x01); ``` DCS command 0x03 with value 0x01 enables compression mode on the panel. Thi= s is placed correctly at the top of the `_on()` function before other initi= alization =E2=80=94 good. **PPS transmission:** ```c + drm_dsc_pps_payload_pack(&pps, dsi->dsc); + mipi_dsi_picture_parameter_set_multi(&dsi_ctx, &pps); ``` Placed after display-on and the 20ms delay. This follows the pattern of oth= er DSC-enabled panel drivers (`panel-visionox-r66451`, `panel-lg-sw43408`, = etc.). **Minor observation (non-blocking):** The existing driver already has a har= dcoded PPS-like blob written to vendor register 0x70 (line 64 in the curren= t source). That blob's decoded parameters (DSC 1.2, slice 40x540, 1080x2400= ) match the new structured DSC config exactly. It would be worth confirming= that both the vendor register write and the standard MIPI PPS are needed = =E2=80=94 but this is common for Qualcomm-reference panels and is almost ce= rtainly correct. **Verdict:** Looks correct. No issues. --- Generated by Claude Code Patch Reviewer