From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/amd/display: Increase DCN314 SR latency by 1us
Date: Mon, 16 Mar 2026 12:18:56 +1000 [thread overview]
Message-ID: <review-patch1-KUZPR04MB9265F4DDEF7627D2E3747BBBE645A@KUZPR04MB9265.apcprd04.prod.outlook.com> (raw)
In-Reply-To: <KUZPR04MB9265F4DDEF7627D2E3747BBBE645A@KUZPR04MB9265.apcprd04.prod.outlook.com>
Patch Review
**Correctness:** The patch consistently updates all relevant locations:
1. **`dcn314_clk_mgr.c`** — The `lpddr5_wm_table` has all four watermark entries (WM_A through WM_D) updated identically:
- `sr_exit_time_us`: 30.0 → 31.0
- `sr_enter_plus_exit_time_us`: 32.0 → 33.0
This is correct — the difference between `sr_enter_plus_exit_time_us` and `sr_exit_time_us` remains 2.0μs (i.e., the enter time alone is still 2μs), which preserves the original relationship.
2. **`dcn314_fpu.c`** — The `dcn3_14_soc` bounding box is updated:
- `sr_exit_time_us`: 16.5 → 17.5
- `sr_enter_plus_exit_time_us`: 18.5 → 19.5
Again, the 2μs delta between enter+exit and exit-only is preserved.
**Observations:**
- The DDR5 table (`ddr5_wm_table` at line 410) is **not** modified — only the LPDDR5 table is changed. This is consistent with the commit message stating the issue is specific to LPDDR5 modules. However, the soc bounding box values in `dcn314_fpu.c` are global (not memory-type-specific), so both DDR5 and LPDDR5 paths will see the increased latency from the FPU side. This seems intentional as a conservative safety margin, but the reviewer may want to confirm the author considered whether the FPU change could affect DDR5 configurations.
- The `Fixes:` tag references a freedesktop.org GitLab issue rather than a commit SHA. This is non-standard for the kernel — typically a `Fixes:` tag references a commit that introduced the bug (format: `Fixes: <sha1> ("commit subject")`). If this is intended for stable backports, a proper `Fixes:` tag with a commit hash would be needed. If the issue just tracks the bug report, consider using `Link:` or `Closes:` instead.
- The patch lacks a `Cc: stable@vger.kernel.org` tag, which would be appropriate if this is meant to fix a user-visible regression.
**Nit:** The commit message `[Why & How]` marker is an AMD-internal convention — no issue, just noting it.
**Verdict:** The change itself looks correct and safe. The main feedback items are:
1. Fix the `Fixes:` tag to reference a commit hash (or change to `Link:`/`Closes:`)
2. Confirm the FPU bounding box change (which affects all memory types) is intentional
3. Consider adding `Cc: stable@vger.kernel.org` if this should be backported
---
Generated by Claude Code Patch Reviewer
prev parent reply other threads:[~2026-03-16 2:18 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-13 15:14 [PATCH] drm/amd/display: Increase DCN314 SR latency by 1us Zhang Zhenzhe
2026-03-16 2:18 ` Claude review: " Claude Code Review Bot
2026-03-16 2:18 ` Claude Code Review Bot [this message]
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