From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/i915/color: Add color pipeline support for SDR planes Date: Mon, 09 Mar 2026 08:26:54 +1000 Message-ID: In-Reply-To: <20260306165307.3233194-11-chaitanya.kumar.borah@intel.com> References: <20260306165307.3233194-1-chaitanya.kumar.borah@intel.com> <20260306165307.3233194-11-chaitanya.kumar.borah@intel.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review Clean enablement patch =E2=80=94 removes the HDR-only guard in `intel_color= _pipeline_plane_init`. This is the gate that makes SDR pipeline visible to = userspace. Logically correct as the final patch. --- ## Summary of Issues by Severity 1. **Critical**: Patch 3 =E2=80=94 CSC mode register corruption when YUV fo= rmat + CSC_FF are both active on SDR planes 2. **Bug**: Patch 7 =E2=80=94 `drm_color_lut_extract` used instead of `drm_= color_lut32_extract` for 32-bit LUT data 3. **Fragile**: Patches 7/9 =E2=80=94 Hardcoded `plane - 3` offset for SDR = plane register mapping with no bounds checking 4. **Series ordering**: Patch 5 (bugfix with Cc:stable) should be first in = series for clean backporting 5. **Minor**: Patch 1 =E2=80=94 copy-paste doc comment error ("interpolatio= n type" =E2=86=92 "CSC FF type") 6. **Minor**: Patch 8 =E2=80=94 functional change (SEG0 removal) mixed into= refactoring patch --- Generated by Claude Code Patch Reviewer