From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/tyr: Add fields for FAULTSTATUS register Date: Wed, 25 Mar 2026 07:08:44 +1000 Message-ID: In-Reply-To: <20260323-b4-tyr-use-register-macro-v3-v3-10-a87daf9e4701@collabora.com> References: <20260323-b4-tyr-use-register-macro-v3-v3-0-a87daf9e4701@collabora.com> <20260323-b4-tyr-use-register-macro-v3-v3-10-a87daf9e4701@collabora.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review The `MmuExceptionType` enum has a comprehensive set of fault codes matching= the ARM Mali MMU fault types. The `MmuAccessType` is identical in semantic= s to the GPU-level `AccessType` from patch 1 =E2=80=93 both are 2-bit field= s with the same values (Atomic/Execute/Read/Write). Consider whether these = could share a type, though keeping them separate is also reasonable since t= hey're in different register pages/modules. One minor observation: the MMU `FAULTSTATUS` here omits bits 10-15 (no `add= ress_valid`, `jasid_valid`, `jasid` fields), unlike the GPU-level `GPU_FAUL= TSTATUS` which defines those fields. If the MMU per-AS fault status registe= r also has these fields in the hardware, they should be added for completen= ess. --- Generated by Claude Code Patch Reviewer