From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/tidss: Add support for DPIENABLE bit Date: Thu, 23 Apr 2026 09:45:59 +1000 Message-ID: In-Reply-To: <20260420-beagley-ai-display-v1-10-f628543dfd14@ideasonboard.com> References: <20260420-beagley-ai-display-v1-0-f628543dfd14@ideasonboard.com> <20260420-beagley-ai-display-v1-10-f628543dfd14@ideasonboard.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review Clean implementation. The feature flag `has_vp_control_dpienable` is only s= et for AM62L. The enable/disable sequence in `dispc_vp_enable()`/`dispc_vp_= disable()` is correct =E2=80=94 DPIENABLE is set before VP enable and clear= ed after VP disable. The `dispc_vp_init()` change to disable DPIENABLE for all VPs at resume tim= e is good defensive programming. ```c #define DISPC_VP_CONTROL_DPIENABLE_MASK GENMASK(6, 6) ``` Using `GENMASK(6, 6)` for a single bit is fine and consistent with the exis= ting style (`GENMASK(0, 0)` for ENABLE). No issues. --- Generated by Claude Code Patch Reviewer