From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/tidss: Add support for DPIENABLE bit Date: Sat, 16 May 2026 12:00:17 +1000 Message-ID: In-Reply-To: <20260513-beagley-ai-display-v2-10-9e9bcefde6bc@ideasonboard.com> References: <20260513-beagley-ai-display-v2-0-9e9bcefde6bc@ideasonboard.com> <20260513-beagley-ai-display-v2-10-9e9bcefde6bc@ideasonboard.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review Clean implementation. Enables DPIENABLE before VP enable, disables after VP disable. Only applies to DPI outputs on SoCs with `has_vp_control_dpienable` (currently only AM62L). The `dispc_vp_init()` change to disable DPIENABLE on all VPs at resume time provides a clean default state. **Nit**: `GENMASK(6, 6)` works but `BIT(6)` would be more idiomatic for a single-bit field. This is purely stylistic. --- Generated by Claude Code Patch Reviewer