From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: dt-bindings: display: renesas, rzg2l-du: Add support for RZ/G3E SoC Date: Sun, 12 Apr 2026 12:45:57 +1000 Message-ID: In-Reply-To: <8f814f22ff62dcde6153260e2c8c29a5415c9a89.1775636898.git.tommaso.merciai.xr@bp.renesas.com> References: <8f814f22ff62dcde6153260e2c8c29a5415c9a89.1775636898.git.tommaso.merciai.xr@bp.renesas.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review Extends the DU bindings to support 4 ports and adds the RZ/G3E compatible. **Issue**: The binding requires `port@0` and `port@3` for RZ/G3E: ```yaml required: - port@0 - port@3 ``` The cover letter says LCDC0 supports DSI + LVDS (single/dual), LCDC1 suppor= ts DSI + LVDS (single) + RGB. Requiring port@3 (LVDS1) seems restrictive = =E2=80=94 what if a board only connects DSI and nothing else? port@0 (DSI) = being required makes sense, but port@3 as required may be overly constraini= ng. Unless the hardware always requires LVDS channel 1 to be described, thi= s could be relaxed. **Also**: `port@2: false` and `port@3: false` are correctly added to RZ/V2H= (P), RZ/G2{L,LC}, and RZ/G2UL conditional blocks. This is good. --- Generated by Claude Code Patch Reviewer