From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: dt-bindings: display: bridge: renesas, dsi: Add support for RZ/G3E SoC Date: Sun, 12 Apr 2026 12:45:58 +1000 Message-ID: In-Reply-To: <0beed64c1cbdb6383bc5da5da3e4b2956ffce5e8.1775636898.git.tommaso.merciai.xr@bp.renesas.com> References: <0beed64c1cbdb6383bc5da5da3e4b2956ffce5e8.1775636898.git.tommaso.merciai.xr@bp.renesas.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review Major restructuring of the DSI bridge bindings. This moves from inline cloc= k descriptions to per-SoC conditional blocks. **Issue 1 (binding correctness)**: The `data-lanes` required constraint was= previously at the top level under port@1 for all SoCs. Now it's been moved= into per-SoC conditional blocks. The `else` branch handles non-RZ/G3E SoCs: ```yaml else: properties: ports: properties: port@1: properties: endpoint: properties: data-lanes: true required: - data-lanes ``` This looks correct for maintaining backward compatibility. **Issue 2**: For RZ/G3E, the binding defines three ports (`port@0`, `port@1= `, `port@2`) with `port@2` being the output port with `data-lanes`. However= , `port@1` explicitly says `data-lanes: false`. This makes sense =E2=80=94 = port@0 and port@1 are inputs from DU0 and DU1 respectively, port@2 is the D= SI output. **Note**: The clock-names for RZ/G3E include `vclk2` as a 6th clock, which = is consistent with the driver changes in patches 13-14. --- Generated by Claude Code Patch Reviewer