From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/tyr: Add fields for TRANSCFG register
Date: Wed, 25 Mar 2026 07:08:44 +1000 [thread overview]
Message-ID: <review-patch11-20260323-b4-tyr-use-register-macro-v3-v3-11-a87daf9e4701@collabora.com> (raw)
In-Reply-To: <20260323-b4-tyr-use-register-macro-v3-v3-11-a87daf9e4701@collabora.com>
Patch Review
Large patch defining the TRANSCFG register fields. The `AddressSpaceMode`, `InaBits`, `PtwMemattr`, and `PtwShareability` enums are well documented.
The `#[allow(clippy::enum_variant_names)]` on `PtwShareability` is appropriate since all variants end in "Shareable".
The TRANSCFG field layout has a gap: bits 4-5 (between `mode` 3:0 and `ina_bits` 10:6) and bits 11-13, 19-21, 23, 26-27, 31-32, 37-59 are undefined/reserved. This is fine – the `register!` macro handles gaps correctly.
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Generated by Claude Code Patch Reviewer
next prev parent reply other threads:[~2026-03-24 21:08 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-24 0:18 [PATCH v3 00/12] drm/tyr: Use register! macro Deborah Brouwer
2026-03-24 0:18 ` [PATCH v3 01/12] drm/tyr: Use register! macro for GPU_CONTROL Deborah Brouwer
2026-03-24 9:56 ` Boris Brezillon
2026-03-24 11:23 ` Danilo Krummrich
2026-03-24 12:06 ` Boris Brezillon
2026-03-24 17:31 ` Danilo Krummrich
2026-03-24 18:15 ` Boris Brezillon
2026-03-24 19:03 ` Danilo Krummrich
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
2026-03-24 0:18 ` [PATCH v3 02/12] drm/tyr: Print GPU_ID without filtering Deborah Brouwer
2026-03-24 9:54 ` Boris Brezillon
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
2026-03-24 0:18 ` [PATCH v3 03/12] drm/tyr: Set interconnect coherency during probe Deborah Brouwer
2026-03-24 9:55 ` Boris Brezillon
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
2026-03-24 0:18 ` [PATCH v3 04/12] drm/tyr: Use register! macro for JOB_CONTROL Deborah Brouwer
2026-03-24 10:00 ` Boris Brezillon
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
2026-03-24 0:18 ` [PATCH v3 05/12] drm/tyr: Use register! macro for MMU_CONTROL Deborah Brouwer
2026-03-24 10:01 ` Boris Brezillon
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
2026-03-24 0:18 ` [PATCH v3 06/12] drm/tyr: Remove custom register struct Deborah Brouwer
2026-03-24 10:02 ` Boris Brezillon
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
2026-03-24 0:18 ` [PATCH v3 07/12] drm/tyr: Add MMU address space registers Deborah Brouwer
2026-03-24 10:03 ` Boris Brezillon
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
2026-03-24 0:18 ` [PATCH v3 08/12] drm/tyr: Add fields for MEMATTR register Deborah Brouwer
2026-03-24 10:05 ` Boris Brezillon
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
2026-03-24 0:18 ` [PATCH v3 09/12] drm/tyr: Add fields for COMMAND register Deborah Brouwer
2026-03-24 10:09 ` Boris Brezillon
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
2026-03-24 0:18 ` [PATCH v3 10/12] drm/tyr: Add fields for FAULTSTATUS register Deborah Brouwer
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
2026-03-24 0:18 ` [PATCH v3 11/12] drm/tyr: Add fields for TRANSCFG register Deborah Brouwer
2026-03-24 21:08 ` Claude Code Review Bot [this message]
2026-03-24 0:18 ` [PATCH v3 12/12] drm/tyr: Add DOORBELL_BLOCK registers Deborah Brouwer
2026-03-24 10:10 ` Boris Brezillon
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
2026-03-24 10:58 ` [PATCH v3 00/12] drm/tyr: Use register! macro Alice Ryhl
2026-03-24 12:35 ` Boris Brezillon
2026-03-24 21:08 ` Claude review: " Claude Code Review Bot
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