From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/tyr: Add fields for TRANSCFG register Date: Wed, 25 Mar 2026 07:08:44 +1000 Message-ID: In-Reply-To: <20260323-b4-tyr-use-register-macro-v3-v3-11-a87daf9e4701@collabora.com> References: <20260323-b4-tyr-use-register-macro-v3-v3-0-a87daf9e4701@collabora.com> <20260323-b4-tyr-use-register-macro-v3-v3-11-a87daf9e4701@collabora.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review Large patch defining the TRANSCFG register fields. The `AddressSpaceMode`, = `InaBits`, `PtwMemattr`, and `PtwShareability` enums are well documented. The `#[allow(clippy::enum_variant_names)]` on `PtwShareability` is appropri= ate since all variants end in "Shareable". The TRANSCFG field layout has a gap: bits 4-5 (between `mode` 3:0 and `ina_= bits` 10:6) and bits 11-13, 19-21, 23, 26-27, 31-32, 37-59 are undefined/re= served. This is fine =E2=80=93 the `register!` macro handles gaps correctly. --- Generated by Claude Code Patch Reviewer