From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: gpu: nova-core: mm: Add MMU v3 page table types Date: Tue, 28 Apr 2026 15:32:01 +1000 Message-ID: In-Reply-To: <20260425211454.174696-12-joelagnelf@nvidia.com> References: <20260425211454.174696-1-joelagnelf@nvidia.com> <20260425211454.174696-12-joelagnelf@nvidia.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review Adds Hopper+ MMU v3 types with PCF (Page Classification Field), unified 40-bit address field, and 6-level page tables. Good parallel structure to v2. **Note:** `DualPdeBig::table_frame` stores a pre-shifted (256-byte aligned) address rather than a `Pfn`, creating API asymmetry with `Pde`. The manual `<< 8` shift in `table_vram_address()` is correct but worth a comment. The `unsafe impl Zeroable for DualPde` should ideally derive `Zeroable` if possible rather than using an unsafe impl, though the safety argument is sound. --- Generated by Claude Code Patch Reviewer