From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/a6xx+: Add support to configure perfcntrs Date: Tue, 05 May 2026 08:06:03 +1000 Message-ID: In-Reply-To: <20260504190751.61052-12-robin.clark@oss.qualcomm.com> References: <20260504190751.61052-1-robin.clark@oss.qualcomm.com> <20260504190751.61052-12-robin.clark@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review The `a6xx_perfcntr_configure()` function programs SEL registers via the rin= gbuffer and writes a `perfcntr_fence` to signal completion. The code correc= tly handles pipe switching for BR/BV/BOTH threads. The `sel_fence` field added to `msm_perfcntr_stream` is used to gate sampli= ng =E2=80=94 the sample_worker checks `memptrs->perfcntr_fence !=3D stream-= >sel_fence` before collecting data. Good design to avoid sampling stale cou= nter configurations. The `perfcntr_fence` field added to `msm_rbmemptrs` is fine =E2=80=94 it's = appended at the end of the struct. --- Generated by Claude Code Patch Reviewer