From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/a6xx+: Add support to configure perfcntrs Date: Thu, 07 May 2026 13:19:05 +1000 Message-ID: In-Reply-To: <20260506171127.133572-12-robin.clark@oss.qualcomm.com> References: <20260506171127.133572-1-robin.clark@oss.qualcomm.com> <20260506171127.133572-12-robin.clark@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review **Status: Minor issue** Implements `a6xx_perfcntr_configure()` which writes SEL register values from the ringbuffer, handling BR/BV/BOTH apertures for a7xx+. **Issue: Assumes contiguous SEL registers** ```c const struct msm_perfcntr_counter *counter = &group->counters[base]; unsigned nr = group_state->allocated_counters; OUT_PKT4(ring, counter->select_reg, nr); ``` This emits a single PKT4 write starting at `counter->select_reg` for `nr` consecutive registers. This assumes that the SEL registers for all counters in a group are contiguous, which is typical for Adreno but not explicitly validated. If the JSON tables ever define non-contiguous SEL registers within a group, this would silently write to wrong registers. The assumption is reasonable for current hardware but could use a comment. --- Generated by Claude Code Patch Reviewer