From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/tidss: oldi: Fix OLDI signal polarities Date: Sat, 16 May 2026 12:00:17 +1000 Message-ID: In-Reply-To: <20260513-beagley-ai-display-v2-11-9e9bcefde6bc@ideasonboard.com> References: <20260513-beagley-ai-display-v2-0-9e9bcefde6bc@ideasonboard.com> <20260513-beagley-ai-display-v2-11-9e9bcefde6bc@ideasonboard.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review Good fix. Removes the unused/ignored `drm_bridge_timings`, adds proper `atomic_check` to set bus flags, and makes `OLDI_DEPOL` conditional on `DRM_BUS_FLAG_DE_LOW`. **Question**: The `atomic_check` unconditionally sets `DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE`. The commit message says the TRM states DSS interfaces on rising edge. Should there also be `DRM_BUS_FLAG_DE_HIGH` set here as the default, since the previous `drm_bridge_timings` had it? The patch relies on `DE_LOW` not being set by default (it won't be if no upstream bridge sets it), so this should be fine in practice, but it might be worth an explicit `DRM_BUS_FLAG_DE_HIGH` for clarity. No blocking issues. --- Generated by Claude Code Patch Reviewer