From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/a6xx+: Add support to configure perfcntrs Date: Sat, 16 May 2026 10:50:10 +1000 Message-ID: In-Reply-To: <20260514134052.361771-12-robin.clark@oss.qualcomm.com> References: <20260514134052.361771-1-robin.clark@oss.qualcomm.com> <20260514134052.361771-12-robin.clark@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review Implements `a6xx_perfcntr_configure()` which programs SEL registers from the ringbuffer, supporting pipe-specific aperture switching (BR/BV/BOTH). **Issue: `OUT_PKT4` with contiguous register assumption.** The code does: ```c OUT_PKT4(ring, counter->select_reg, nr); for (unsigned c = 0; c < nr; c++) OUT_RING(ring, group_state->countables[c]); ``` This assumes that the SEL registers within a group are contiguous starting from `counter->select_reg`. This should be true by construction of the perfcntr tables, but it's worth noting as an implicit contract. The `perfcntr_fence` write via `CP_MEM_WRITE` and the preempt trigger are correct. --- Generated by Claude Code Patch Reviewer