From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/tidss: oldi: Fix OLDI signal polarities Date: Thu, 04 Jun 2026 16:54:12 +1000 Message-ID: In-Reply-To: <20260529-beagley-ai-display-v3-11-7fefdc5d1adf@ideasonboard.com> References: <20260529-beagley-ai-display-v3-0-7fefdc5d1adf@ideasonboard.com> <20260529-beagley-ai-display-v3-11-7fefdc5d1adf@ideasonboard.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review Good cleanup. Removes the unused `drm_bridge_timings`, adds proper `atomic_check` to set input bus flags (sample on rising edge), and makes OLDI_DEPOL conditional on DRM_BUS_FLAG_DE_LOW. The `atomic_check` implementation correctly clears NEGEDGE before setting POSEDGE: ```c + bridge_state->input_bus_cfg.flags &= + ~(DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | + DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE); + bridge_state->input_bus_cfg.flags |= + DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE | + DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE; ``` The patch also correctly adds `DRM_BUS_FLAG_DE_LOW` handling based on the input bus cfg flags. The commit message is honest about testing limitations. No issues found. --- Generated by Claude Code Patch Reviewer