From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/a8xx: Add perfcntr flush sequence Date: Thu, 23 Apr 2026 09:13:16 +1000 Message-ID: In-Reply-To: <20260420222621.417276-13-robin.clark@oss.qualcomm.com> References: <20260420222621.417276-1-robin.clark@oss.qualcomm.com> <20260420222621.417276-13-robin.clark@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review Adds `a8xx_perfcntr_flush()` which writes flush commands and polls for completion. Clean and straightforward. Minor: Only the unsliced flush status (`RBBM_PERFCTR_FLUSH_HOST_STATUS`) is polled, but the sliced flush (`RBBM_SLICE_PERFCTR_FLUSH_HOST_CMD`) is also issued. Is there a separate slice flush status register that should also be polled, or does the single status bit cover both? --- Generated by Claude Code Patch Reviewer