From mboxrd@z Thu Jan  1 00:00:00 1970
From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/msm/a8xx: Add perfcntr flush sequence
Date: Tue, 05 May 2026 08:06:03 +1000
Message-ID: <review-patch12-20260504190751.61052-13-robin.clark@oss.qualcomm.com>
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Patch Review

Clean a8xx-specific flush implementation:

```c
gpu_write(gpu, REG_A8XX_RBBM_PERFCTR_FLUSH_HOST_CMD, BIT(0));
gpu_write(gpu, REG_A8XX_RBBM_SLICE_PERFCTR_FLUSH_HOST_CMD, BIT(0));
wmb();
if (gpu_poll_timeout(...)) { dev_err(...); }
```

The `wmb()` before polling is correct. The 100us poll interval and 100ms ti=
meout are reasonable. Only wired up for a8xx, not a6xx/a7xx =E2=80=94 that'=
s expected since the flush mechanism differs per generation.

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