From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/a8xx: Add perfcntr flush sequence Date: Thu, 07 May 2026 13:19:06 +1000 Message-ID: In-Reply-To: <20260506171127.133572-13-robin.clark@oss.qualcomm.com> References: <20260506171127.133572-1-robin.clark@oss.qualcomm.com> <20260506171127.133572-13-robin.clark@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review **Status: Minor issue** Adds `a8xx_perfcntr_flush()` which flushes slice/unslice counters to perf RAM before reading. **Observation:** The function only checks `RBBM_PERFCTR_FLUSH_HOST_STATUS` but not the slice flush status. Is there a separate status register for `RBBM_SLICE_PERFCTR_FLUSH_HOST_CMD`, or does the single status register cover both? --- Generated by Claude Code Patch Reviewer