From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/a8xx: Add perfcntr flush sequence Date: Sat, 16 May 2026 15:20:24 +1000 Message-ID: In-Reply-To: <20260511130017.96867-13-robin.clark@oss.qualcomm.com> References: <20260511130017.96867-1-robin.clark@oss.qualcomm.com> <20260511130017.96867-13-robin.clark@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review The flush writes to both `RBBM_PERFCTR_FLUSH_HOST_CMD` and `RBBM_SLICE_PERFCTR_FLUSH_HOST_CMD`, but only polls `RBBM_PERFCTR_FLUSH_HOST_STATUS`. Is there a separate status register for the slice flush that should also be polled, or does the single status register cover both? Worth confirming that the slice flush doesn't have its own independent completion status. --- Generated by Claude Code Patch Reviewer