From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/bridge: tc358762: Set DE_POL and DCLK_POL properly Date: Sat, 16 May 2026 12:04:24 +1000 Message-ID: In-Reply-To: <20260513-tc358762-fixes-v3-12-6698b55008b9@ideasonboard.com> References: <20260513-tc358762-fixes-v3-0-6698b55008b9@ideasonboard.com> <20260513-tc358762-fixes-v3-12-6698b55008b9@ideasonboard.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review Instead of hardcoding `LCDCTRL_DCLK_POL`, reads `bridge_state->output_bus_cfg.flags` to determine pixel clock edge and DE polarity. This makes the driver responsive to panel DT bus-flags. For the existing `powertip_ph800480t013_idf02` panel which has: ```c .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, ``` `DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE` means the panel samples on negedge, so the bridge should *drive* on posedge (`DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE`). The `output_bus_cfg.flags` should reflect the panel's requirements after negotiation. With `DRM_BUS_FLAG_DE_HIGH`, `DE_POL` won't be set (active-high DE is the default when the bit is clear), which is correct. Minor typo in the commit message: "actuall" should be "actually": ``` ignoring what the panel actuall wants ``` Otherwise correct. **Reviewed-by worthy** with the typo fix. --- Generated by Claude Code Patch Reviewer