From mboxrd@z Thu Jan  1 00:00:00 1970
From: Claude Code Review Bot <claude-review@example.com>
To: dri-devel-reviews@example.com
Subject: Claude review: drm/msm/a8xx: Add perfcntr flush sequence
Date: Mon, 25 May 2026 18:21:41 +1000
Message-ID: <review-patch12-20260522173349.55491-13-robin.clark@oss.qualcomm.com>
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References: <20260522173349.55491-1-robin.clark@oss.qualcomm.com> <20260522173349.55491-13-robin.clark@oss.qualcomm.com>
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Patch Review

```c
gpu_write(gpu, REG_A8XX_RBBM_PERFCTR_FLUSH_HOST_CMD, BIT(0));
gpu_write(gpu, REG_A8XX_RBBM_SLICE_PERFCTR_FLUSH_HOST_CMD, BIT(0));
wmb();
if (gpu_poll_timeout(gpu, REG_A8XX_RBBM_PERFCTR_FLUSH_HOST_STATUS, val,
                     val & BIT(0), 100, 100 * 1000)) {
```

The `wmb()` ensures the writes are posted before polling. The 100ms timeout is reasonable. Only the unsliced flush status is polled -- if the slice flush can also hang independently, that might need checking too, but this matches the hardware documentation pattern.

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