From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/a8xx: Implement IFPC support for A840 Date: Wed, 25 Mar 2026 07:32:11 +1000 Message-ID: In-Reply-To: <20260324-a8xx-gpu-batch2-v1-13-fc95b8d9c017@oss.qualcomm.com> References: <20260324-a8xx-gpu-batch2-v1-0-fc95b8d9c017@oss.qualcomm.com> <20260324-a8xx-gpu-batch2-v1-13-fc95b8d9c017@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review Large patch adding pwrup/ifpc/dynamic register lists and the `a8xx_patch_pwrup_reglist()` function. **Key change:** `a8xx_flush()` now uses `a6xx_fenced_write()` for `CP_RB_WPTR` instead of plain `gpu_write()`. This is needed for IFPC to ensure the GPU is awake. The `a8xx_patch_pwrup_reglist()` function follows the same pattern as the A7xx version. The register lists are large but this is expected for IFPC support. **CP_INIT change:** `BIT(8)` is added to enable the register init list with spinlock. Three new `OUT_RING` calls add the reglist address and dynamic list enablement. This should be verified against the CP_INIT packet format for A8xx. --- Generated by Claude Code Patch Reviewer