From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/i915/psr: Program Panel Replay CONFIG3 using AS SDP transmission time Date: Thu, 12 Mar 2026 06:55:31 +1000 Message-ID: In-Reply-To: <20260311113611.3393194-15-ankit.k.nautiyal@intel.com> References: <20260311113611.3393194-1-ankit.k.nautiyal@intel.com> <20260311113611.3393194-15-ankit.k.nautiyal@intel.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review **BUG:** This patch extends the burst write buffer from 2 to 3 bytes: ```c u8 buf[3]; ... buf[0] = panel_replay_config; // -> PANEL_REPLAY_CONFIG (0x1b0) buf[1] = panel_replay_config2; // -> PANEL_REPLAY_CONFIG2 (0x1b1) buf[2] = panel_replay_config3; // -> 0x1b2 (WRONG!) ``` But `PANEL_REPLAY_CONFIG3` is defined (in patch 4) at DPCD address **0x11a**, not at 0x1b2. The burst write starting at `PANEL_REPLAY_CONFIG` (0x1b0) will write `panel_replay_config3` to address 0x1b2, which is an entirely different (and possibly reserved) DPCD register. **CONFIG3 must be written separately with its own `drm_dp_dpcd_writeb()` call to address 0x11a.** --- Generated by Claude Code Patch Reviewer