From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/exynos: exynos_dp: Apply analogix_dp_finish_probe() Date: Sun, 22 Mar 2026 04:35:48 +1000 Message-ID: In-Reply-To: <20260319074744.1965918-1-damon.ding@rock-chips.com> References: <20260319071452.1961274-1-damon.ding@rock-chips.com> <20260319074744.1965918-1-damon.ding@rock-chips.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Patch Review Simplifies Exynos probe similarly. The logic to check `of_get_display_timin= gs()` first and fall back to `analogix_dp_finish_probe()` is correct =E2=80= =94 the display-timings path creates a bridge upfront, so no need for the a= ux bus probe path. The `if (dp->plat_data.panel || dp->plat_data.next_bridge)` / `else` logic = at the end of probe is clear: if we already have a panel or bridge (from di= splay-timings), add the component directly; otherwise use finish_probe to d= iscover via aux bus. Nit: The `else` clause could be simplified by removing the `else` keyword s= ince the `if` branch returns. No blocking issues. --- Generated by Claude Code Patch Reviewer