From mboxrd@z Thu Jan 1 00:00:00 1970 From: Claude Code Review Bot To: dri-devel-reviews@example.com Subject: Claude review: drm/msm/a6xx: Enable Preemption on X2-85 Date: Wed, 25 Mar 2026 07:32:11 +1000 Message-ID: In-Reply-To: <20260324-a8xx-gpu-batch2-v1-15-fc95b8d9c017@oss.qualcomm.com> References: <20260324-a8xx-gpu-batch2-v1-0-fc95b8d9c017@oss.qualcomm.com> <20260324-a8xx-gpu-batch2-v1-15-fc95b8d9c017@oss.qualcomm.com> X-Mailer: Claude Code Patch Reviewer Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 Patch Review Adds `x285_dyn_pwrup_reglist` and enables preemption for X2-85. **Observation:** The `x285_dyn_pwrup_reglist_regs` is almost identical to `a840_dyn_pwrup_reglist_regs` from patch 13. The differences are: - X2-85 is missing `REG_A6XX_RB_DBG_ECO_CNTL` and `REG_A6XX_RB_RBP_CNTL` entries that A840 has with `BIT(PIPE_BV)|BIT(PIPE_BR)`, and X2-85 `REG_A6XX_RB_RBP_CNTL` only has `BIT(PIPE_BR)`. The X2-85 also reuses `a840_pwrup_reglist` and `a840_ifpc_reglist` which is fine. --- Generated by Claude Code Patch Reviewer